Static Random Access Memory (SRAM) arrays occupy a large fraction of the chip area in many of today's memory designs. As memory will continue to consume a large fraction of many future designs, scaling of memory density involves continuing to track the scaling trends of logic. With aggressive scaling of metal oxide semiconductor field effect transistors (MOSFETs), leakage currents are increasing with each circuit node.
These leakage currents consume a significant amount of power. One approach to reduce leakage currents MOSFET circuitry includes powering down portions of the MOSFET chip circuitry when not in use. However, this approach cannot be applied in certain memory arrays, e.g., an SRAM array, without losing the stored contents of the memory.